Memory devices, testing systems and methods

ABSTRACT

Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.12/721,346, filed Mar. 10, 2010, and issued as U.S. Pat. No. 8,429,470on Apr. 23, 2013. This application and patent are incorporated herein byreference in their entirety and for any purpose.

TECHNICAL FIELD

Embodiments of this invention relate to memory devices, and, moreparticularly to memory devices having on-board test capabilities as wellas testing methods and systems.

BACKGROUND

During the fabrication of integrated circuits such as memory devices, itis conventional to test such integrated circuits at several stagesduring the fabrication process. For example, after fabrication,integrated circuits may be connected to a tester with a probe card whenthe integrated circuits are still in wafer form. In a final testoccurring after the integrated circuits have been diced from the waferand packaged, the integrated circuits may be placed into sockets on aload board or other device and once again tested.

As is well-known in the art, memory devices may be provided withcircuitry that allows limited repair of defects in the memory devices.Such repair devices may allow defects to be repaired at specificaddresses. Once the addresses that include a defect have been determined(i.e., once the address at which respective defects are located havebeen obtained by testing), the defects may then be repaired.

Memory devices are conventionally tested during fabrication and afterpackaging using high-speed automated testers. The testers typicallyhaving a single data input/output (“I/O”) bus, which is normally coupledto several memory devices during a test. Although data may besimultaneously written to all of the memory devices, data may not besimultaneously read from all of the memory devices or else severalmemory devices may simultaneously apply read data to the I/O bus of thetester. To avoid this bus contention problem, data may be read from eachof the memory devices in sequence, thereby requiring multiple readcycles to read the data from all of the memory devices. Further,conventional testers for memory devices are very expensive, and using aseparate tester to test each memory device individually would require avery large number of testers in a high volume memory device fabricationenvironment. To limit the cost of memory device testing, memory testersmay test a large number of devices in parallel. In these situations, atester may transmit write commands, addresses and data to a large numberof memory devices in parallel, thus writing the same data to the samelocations in all of the memory devices. The memory devices may then readto determine if the read data matches the write data. If the data readat any address does not match the data written to that address, then adefect at that address is considered to exist.

One problem with testing memory devices using the above-describedtechniques is that it may be necessary to read data from each memorydevice individually to determine if data read from each address is inerror. Doing so can greatly limit the rate at which a tester can testmemory devices. As a result, attempts have been made to provide memorydevices with limited on-board test capabilities. One approach has beento provide comparison circuitry in the memory device itself to avoid theneed to couple read data from the memory device for evaluation. A largenumber of memory devices may be coupled to a tester in parallel. Thetester may simultaneously write data to each address in all of thememory devices, and the memory device subsequently compares the datawritten to each address with the data read from that address. In anotherapproach, bits of the data read responsive to a memory request may becompared to each other to detect and error, or the correct comparisonbits may be supplied to the memory devices by the tester with the readcommands. In any case, a bit indicative of an error can be stored in anon-board storage device, such as a latch. Address bits corresponding tothe location of the defect causing the error can also be stored in anon-board storage device. The on-board storage devices can then be readat the conclusion of the test to determine the addresses where errorshave been detected, and those addresses can then be repaired byconventional means. Unfortunately, it can require a significant numberof storage devices, such as latches, to store all of the address bitsfor each of a large number of addresses that are to be repaired byconventional means. As a result, the storage capacity and/or cost ofmemory devices can be adversely affected by the need to provide a largeamount of circuitry to store error data.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart showing a read-modify-write test procedureaccording to one embodiment.

FIG. 2 is a block diagram of a write mask system according to oneembodiment.

FIG. 3 is a logic diagram of a portion of a write mask circuit accordingto another embodiment.

FIG. 4 is a block diagram of the remaining portion of the write maskcircuit embodiment of FIG. 3.

FIG. 5 is a block diagram of an embodiment of a memory device that canbe used with various embodiments of a write mask circuit.

DETAILED DESCRIPTION

Various embodiments of memory device testing systems and methods may beused by performing a standard “read-modify-write” test procedure. Oneexample of a suitable read-modify-write procedure 10 is illustrated inFIG. 1. The test starts at 12, and specific data, such as a logic “1”bit, may be written to every memory cell of every memory address in anarray at step 14. The number of memory cells at each address may varyfrom one memory device to another, but it commonly corresponds to anumber of data bus terminals or the product of the number of data busterminals and a number of serial bits that are coupled to or from eachdata bus terminal for each write or read access. An internal addresscounter (not shown) may then be set to the address of a first memorycell at step 16. A read memory operation may then be initiated at thecurrent address at step 18. A determination may then be made at step 2Qwhether all of the read data bits are a “1.” If not, a write mask signalmay be generated at step 22 to preserve the failing state of the datathat would otherwise be written to at the current address, as explainedbelow. If it was determined at step 20 that all of the read data bitswere a “1,” the write mask signal is not generated at step 22 so that a“0” may be written to all memory cells currently being addressed at step25. The process may then advance to step 26 as explained below. If thememory cells being read correctly store the data (e.g., the cells storethe specific data without error), the read data bits will all be “1.” Acheck is then made at step 26 to determine if the read at step 18 was atthe last address in the memory device. If not, the address isincremented at step 27, and the process again progresses through steps18-26 as exampled above.

If the determination is made at step 26 that the last address was read,the current address may be set to the first memory address at step 28.Therefore, if the 4 bits read at step 18 were found to be “1111” at step20, then the data stored at the current address will now be “0000.” Thememory cells at the current address may again be read at step 32. Alogic “0” should normally be read from each of the non-failing memorycells being addressed at step 32 because a “0” was written to all of thenon-failing memory cells at step 25. A determination may be made at step30 whether all of the read data bits are a “Q.” If a “1” is read fromany of the memory cells being addressed in step 30, a write mask signalmay be generated at step 36 to preserve the failing state of the datathat would otherwise be written to at the current address, as explainedbelow. If it was determined at 30 that all of the read data bits were a“0,” the write mask signal is not generated at step 36 so that a “1” maybe written to all memory cells currently being addressed at step 38. Theprocess may advance to step 40 without the memory address being maskedsince there may be no additional writes at the current address that mayrequire masking. On the other hand, if all of the read data bits areread as a “0” at step 30, a “1” may be written to all memory cellscurrently being addressed at step 38. On the other hand, for example, if“1101” was read at an address at step 30, then the data stored at thecurrent address will continue to be “1101.” Thus if the incorrect datawas read at either step 18 or 28, the data bits stored at thecorresponding address should be a combination of “1” and “0” bits. Onthe other hand, if the correct data was read at both step 18 and step28, the data bits stored at the corresponding address should be “1111”after step 38 has been completed. A determination may then be made atstep 40 whether the memory cells being addressed is the last memoryaddress in the array. If not, the address may be incremented at step 44before returning to step 32 where the memory cell corresponding to thenew address may, be read. The above procedure again repeats until adetermination is made at step 40 that the memory cells currently beingaddressed are the last memory cells in the array. After the aboveprocedure has been completed for all memory cells in the array, theentire array may be read at step 46, and the process may then terminateat step 48. Any address that contains any “0” bit may be considered anaddress that may include a defect, and that should be repaired bysuitable means, such as by remapping the address to a redundant row orcolumn of memory cells. Although the particular bit that is storing a“0” may identify a specific defective memory cell at that address, theidentity of the specific defective memory cell may not be required sincememory cell defects may generally be repaired on an address-by-addressbasis rather than a cell-by-cell basis.

It can therefore be seen that, at the conclusion of the test, all of thetest failure data from the test may be stored in the very same arraythat was tested by the read-modify-write test procedure. There may bethus no limit to the amount of test failure data that can be stored, andno additional storage components, such as latches, may be required tostore this failure data. In contrast, as mentioned above, prior artmemory device would trigger a latch or other device at steps 22 and 36to store the address that resulted in the incorrect data being read.Unfortunately, the amount of space consumed on a semiconductor die bythe number of latches needed to store all of the data bits of eachaddress or even each address may preclude a large number of addressesthat include a defect from being stored. As a result, prior artread-modify-write test procedures may sometimes be inadequate.

One embodiment of a system 50 for providing write mask signalsresponsive to detecting a read data error is shown in FIG. 2. Withreference to FIG. 2, the system 50 may receive an active high TM-ENsignal, which transitions high during the “read-modify-write” testprocedure to enable failure data to be stored in the array of memorycells being tested. Thereafter, active high CLK-R and CLK-F signals,which are generally available in conventional memory devices, may beapplied to, the system 50. The CLK-R and CLK-F signals are clock signalsthat may transition high each time a comparison is made in the memorydevice between data written to a memory address during respective risingand falling edges of a write data strobe signal, and corresponding datamay be subsequently read from that same address. The system 50 may alsoreceive active high ERR-R and ERR-F signals, which are also signals thatare available in conventional memory devices to indicate when at leastone of a set of data bits read at respective rising and falling edges ofan internal clock signal is in error. The system 50 may also receiveactive high EN-R and EN-F signals available in conventional memorydevices to indicate when respective rising edge and falling edge readdata has been evaluated by circuitry in the memory device to determineif the read data are in error. Finally, the system 50 may receive theactive high RD signal, which may also be available in conventionalmemory devices to indicate the start of a memory read operation.

In operation, the TM-EN signal may be set high to enable failure data tobe stored in the memory array being tested using a “read-modify-write”test procedure, such as the test procedure shown in FIG. 1. A logic “1”data bit may then be written to all of the memory cells at each memoryaddress of the memory array, as explained above with respect to step 14of FIG. 1. Thereafter, the RD signal may transition high, and data maybe read from the memory cells at the first address of the memory arraybeing tested during either the rising edge or the falling edge of theinternal clock signal. When either the EN-R or the EN-F signal,respectively, transitions high, if any of the data bits read at step 18(FIG. 1) was a low, the ERR-R or ERR-F signal will be active high. Insuch case, the WrMsk signal at the output of the system 50 maytransition high on the rising edge of either the CLK-R or the CLK-Fsignal, respectively. The active high WrMsk signal may be applied toconventional circuitry commonly found in conventional memory devices tomask data from being written to the memory array being tested for aslong as the WrMsk signal is high. Therefore, the writing of a logic “0”to the memory cell being tested at step 26 may be suppressed. The system50 may operate in essentially the same manner when the data bits areread at step 28 (FIG. 1) and data bits may be written at step 38 unlessthe write was masked at step 36.

Although the embodiment exemplified by the system 50 uses a specific setof signals providing specific functions to cause failure data to bestored in the array being tested, it will be understood that otherembodiments may use a fewer or greater number of other signals providingthe same or different functions to cause failure data to be stored inthe array being tested.

An embodiment of the system 50 of FIG. 2 for providing write masksignals is shown in FIGS. 3 and 4. With reference to FIG. 3, a one-shotcircuit 70 includes a NAND gate 74 that receives the RD signal and theTM-EN signal. As explained above, the TM-EN signal may transition toenable the above-described test procedure. The RD signal may transitionhigh at the start of a read operation when data may be read from acurrent address. Thus, when the test mode is enabled, the output of theNAND gate 74 may transition low. This low may be applied directly to oneinput of a NOR gate 78 and to the other input of the NOR gate 78 througha delay circuit 80 and an inverter 84. Before the RD signal hastransitioned high at the start of a read operation, the output of theNAND gate 74 may be high so that the output of the inverter 84 will below. The output of the inverter 84 may remain low for a period becauseof the delay circuit 80 when the output of the NAND 74 transitions lowat the start of a read operation. As a result, the output of the NORgate 78 may transition high for a period determined by the delay of thedelay circuit 80. The output of the NOR gate 78 may be coupled throughtwo inverters 86, 88 to generate a reset (“RST”) signal. Thus, the RSTsignal may pulse high at the start of every read operation.

The RST pulse from the one-shot 70 may be applied to a write maskcircuit 100, which is shown in FIG. 4. More specifically, the RST pulsemay be applied to one input of a NAND gate 104, which also has inputsreceiving the TM-EN signal and a PWRUP signal whenever a supply voltagein the memory device has stabilized. The output of the NAND gate 104 maygenerate an active low clear flag (“CLRFlg”) signal. Therefore, theCLRFlg signal may pulse low responsive to the RST pulse whenever thetest mode is enabled and the supply voltage has stabilized,

With further reference to FIG. 4, the write mask circuit 100 may includea pair of latches 110, 114 each of which has a data (“D”) input. The Dinput of the latch 110 may be coupled to the output of a NAND gate 120through an inverter 124. One input of the NAND gate 120 may receive theCLK-R signal while the other input of the NAND gate 120 may receive theERR-R signal. As explained above with reference to FIG. 2, the CLK-Rsignal is a clock signal that transitions high each time a comparison ismade in the memory device between data written to a memory addressduring a rising edge of a write data strobe signal, and correspondingdata may be subsequently read from that same address. As also explainedabove, the ERR-R is a signal available in conventional memory devices toindicate when at least one of the data bits read responsive to therising edge of an internal clock signal is in error. Thus, if the databeing read from a memory array responsive to the rising edge of aninternal clock signal at an address contains an erroneous data bit, theD input of the latch 110 will transition high at the rising edge of theCLK-R signal.

The D input of the latch 114 may be coupled to circuitry that isidentical to the circuitry to which the D input of the latch 110 iscoupled. Specifically, the D input may be coupled to a NAND gate 130through an inverter 134, the inputs of the NAND gate 130 receive theCLK-F signal and the ERR-F signal. Therefore, if the data being readfrom a memory array responsive to the falling edge of an internal clocksignal at an address contains an erroneous data bit, the D input of thelatch 110 will transition high at the rising edge of the CLK-F signal.

Each of the latches 110, 114 also includes an active high latch inputLat and an active low Latf input which causes a logic level applied to adata D input to be stored in the respective latch 110, 114. The Latfinput of the latch 110 may be coupled to the output of an inverter 140,and the Lat input may be coupled to the output of an inverter 144, whichhas an input coupled to the output of the inverter 140. The input of theinverter 140 receives the EN-R signal, which, as explained above, is asignal that is available in conventional memory devices to indicate whenthe data read responsive to the rising edge of an internal clock signalhas been evaluated by circuitry in the memory device to determine if theread data are in error. Thus, in response to the rising edge of the EN-Rsignal, a logic “0” will be stored in the latch 110 if none of the bitsof the read data is in error, and a logic “1” will be stored in thelatch 110 if any of the bits of the read data is in error. Similarly,The Latf input of the latch 114 may be coupled to the output of aninverter 146, and the Lat input may be coupled to the output of aninverter 148, which has an input coupled to the output of the inverter140. The input of the inverter 146 receives the EN-F signal, which, asexplained above, is a signal that is available in conventional memorydevices to indicate when the data read responsive to the falling edge ofan internal clock signal has been evaluated by circuitry in the memorydevice to determine if the read data are in error. Thus, in response tothe rising edge of the EN-F signal, a logic “0” may be stored in thelatch 114 if none of the bits of the read data is in error, and a logic“1” may be stored in the latch 114 if any of the bits of the read datais in error.

The final input to the latches 110, 114 is an active low reset (“R”)input, which may be coupled to receive the ClrFlg signal from the outputof the NAND gate 104. As explained above, the CLRFlg signal may pulselow responsive to the RST pulse whenever the test mode is enabled andthe supply voltage has stabilized. As also explained above, the RSTpulse may be generated at the start of any memory read operation. Thus,the latches 110, 114 may be reset at the start of any memory readoperation.

The outputs of the latches 110, 114 may be applied to respective inputsof a NOR gate 160. Therefore, if either latch 110, 114 is set responsiveto detecting a read in error, the output of the NOR gate 160 may be low.The output of the NOR gate 160 may be applied to an input of a NAND gate164 which receives the output on a NAND gate 168 at its other input. TheNAND 168 may receive the TM-EN signal through an inverter 170 so thatthe NAND gate 168 is disabled to enable the NAND gate 164 whenever thetest mode is enabled. The other input of the NAND gate 168 may receivean external write mask signal (“ExtWrMsk”), which is normally present inconventional memory devices whenever a write operation is to be masked.Thus, when the test mode is enabled, an active high mask write signal(“WrMsk”) may be generated whenever either of the latches 110, 114 isset responsive to detecting a data read error. When the test mode isinactive, the WrMsk may be generated responsive to the ExtWrMsk signal.As explained above, the WrMsk signal is normally generated inconventional memory devices responsive to the ExtWrMsk write mask signalto mask a data write operation. However, using the write mask circuit100, the WrMsk may also be generated whenever a read data error isdetected during a test procedure, such as the read-modify-write testprocedure 10 shown in FIG. 1.

Various embodiments of the write mask circuit can be used in virtuallyany memory device in which a write mask operation is possible, includingdynamic random access memory (DRAM”) devices, flash memory devices, andstatic random access memory (SRAM”) devices, to name a few. For example,as shown in FIG. 5, a conventional synchronous dynamic random accessmemory (“SDRAM”) 200 may use various embodiments of a write maskcircuit. The operation of the SDRAM 200 is controlled by a commanddecoder 204 responsive to high-level command signals received on acontrol bus 206. The command decoder 204 generates a sequence of commandsignals responsive to the high level command signals to carry out thefunction (e.g., a read or a write) designated by each of the high levelcommand signals. These command signals include the RD signal, whichtransitions active high at the start of read operations. The commanddecoder 204 may also include a mode register 208 that can be programmedto generate the test mode enable TM-EN signal.

The SDRAM 200 includes an address register 212 that receives rowaddresses and column addresses through an address bus 214. The addressbus 214 is generally coupled to a memory controller (not shown in FIG.5). A row address is generally first received by the address register212 and applied to a row address multiplexer 218. The row addressmultiplexer 218 couples the row address to a number of componentsassociated with either of two memory banks 220, 222 depending upon thestate of a bank address bit forming part of the row address. Associatedwith each of the memory banks 220, 222 is a respective row address latch226, which stores the row address, and a row decoder 228, which decodesthe row address and applies corresponding signals to one of the arrays220 or 222. The row address multiplexer 218 also couples row addressesto the row address latches 226 for the purpose of refreshing the memorycells in the arrays 220, 222. The row addresses may be generated forrefresh purposes by a refresh counter 230 which is controlled by arefresh controller 232. The refresh controller 232 is in turn,controlled by the command decoder 204.

After the row address has been applied to the address register 212 andstored in one of the row address latches 226, a column address isapplied to the address register 212. The address register 212 couplesthe column address to a column address latch 240. Depending on theoperating mode of the SDRAM 200, the column address is either coupledthrough a burst counter 242 to a column address buffer 244, or to theburst counter 242, which applies a sequence of column addresses to thecolumn address buffer 244 starting at the column address output by theaddress register 212. In either case, the column address buffer 244applies a column address to a column decoder 248.

Data to be read from one of the arrays 220, 222 is coupled to columncircuitry 250, 252, which may include sense amplifiers, I/O gating, DQM&WPB mask logic, block write col/byte mask logic) for one of the arrays220, 222, respectively. The data bits developed by the sense amplifiersmay then be coupled to a data output register 256. Data to, be writtento one of the arrays 220, 222 may be coupled from the data bus 258through a data input register 260. The write data may be coupled to thecolumn circuitry 250, 252 where they may be transferred to one of thearrays 220, 222, respectively. The memory device 200 also includes adata compare circuit 262 that serves as an error detect circuit bycomparing sets of data bits read from the memory banks 220, 222 todetermine if they all have the same logic level. If not, the datacompare circuit 262 may generate ERR-R and ERR-F signals, as describedabove. The data compare circuit 262 may also generate the CLK-R andCLK-F signals and the EN-R and EN-F signals, which are also describedabove. These signals may be applied to a write mask circuit 264, whichgenerates the WrMsk signal to mask data write operations. The WrMsksignal is applied to a mask register 266 to selectively block the flowof write data to the column circuitry 250, 252.

Although the present invention has been described with reference to thedisclosed embodiments, persons skilled in the art will recognize thatchanges may be made in form and detail without departing from theinvention. Such modifications are well within the skill of thoseordinarily skilled in the art. Accordingly, the invention is not limitedexcept as by the appended claims.

What is claimed is:
 1. An apparatus comprising: error detect circuitryconfigured to provide an error signal having a value indicating an errorresponsive to detecting a read data error associated with a memory cellof an array of memory cells; a write mask circuit configured to providea write mask signal responsive to receiving the error signal having thevalue indicating the error; and the array of memory cells, wherein thearray is configured to store the read data error in the memory cell ofthe array with which the read data error is associated with.
 2. Theapparatus of claim 1, wherein the error detect circuitry is furtherconfigured provide the error signal having a value indicating no errorresponsive to detecting correct read data associated with the memorycell of the array of memory cells.
 3. The apparatus of claim 2, whereinthe write mask circuit is further configured to inhibit provision of awrite mask signal responsive to the error signal have the valueindicating no error.
 4. The apparatus of claim 1, wherein the write maskcircuit is further configured to provide the write mask signal based onan external write mask signal.
 5. The apparatus of claim 1, furthercomprising reset logic configured to provide a reset signal responsiveto a test enable signal, wherein the write mask circuit is configured toreset the write mask signal responsive to the reset signal.
 6. Theapparatus of claim 1, wherein the write mask circuit comprises a latchconfigured to latch an internal write mask signal having a value basedon the error signal, wherein the write mask circuit is configured togenerate the write mask signal based on the internal write mask signal.7. A method comprising: for an address of a plurality of addresses in amemory device: reading first data stored at a memory cell associatedwith the address; determining, with error detect circuitry, whether thefirst data was correctly stored at the memory cell associated with theaddress; if the first data was not correctly stored at the memory cell,masking at a mask circuit subsequent write operations at the address,causing a record of the storage error to be stored at the address; andif the first data was correctly stored at the memory cell, writingsecond data to the memory cell associated with the address.
 8. Themethod of claim 7, further comprising reading data from the memory cell.9. The method of claim 8, wherein determining whether the first data wascorrectly stored at a memory cell comprises comparing the data to thefirst data.
 10. The method of claim 7, wherein masking the subsequentwrite operations at the address comprises providing a write mask signal.11. The method of claim 10, further comprising clearing the write masksignal responsive to a reset signal.
 12. The method of claim 11, furthercomprising clearing the reset signal prior to determining whether thefirst data was correctly stored at a memory cell.
 13. The method ofclaim 7, further comprising writing the first data to the memory cellassociated with the address.
 14. The method of claim 13, determiningwhether the second data was correctly stored at the memory cellassociated with the address.
 15. A method comprising: reading first datastored in an array of memory cells in a memory device corresponding toof memos addresses; determining, with error detect circuitry, whetherthe first data was correctly stored in the array of memory cells in thememory device corresponding to the plurality of memory addresses; andmasking at a mask circuit the writing of second data to masked memorycells of the array of memory cells corresponding to masked addresses ofthe plurality of memory addresses responsive to determining the firstdata was incorrectly stored at the masked memory cells corresponding tothe masked addresses, causing a record of the storage errors to bestored at the masked addresses.
 16. The method of claim 15, furthercomprising writing the first data to the array of memory cellscorresponding to the plurality of memory addresses.
 17. The method ofclaim 15, further comprising writing the second data to unmasked memorycells of the array of memory cells corresponding to unmasked addressesof the plurality of memory addresses.
 18. The method of claim 17,wherein the unmasked addresses are mutually exclusive from the maskedaddresses.
 19. The method of claim 15, further comprising: reading thesecond data written to the array of memory cells in the memory devicecorresponding to the plurality of memory addresses; determining whetherthe second data was correctly stored in the unmasked memory cellscorresponding to the unmasked addresses; and masking writing of thirddata to second masked memory cells of the unmasked memory cellscorresponding to second masked addresses of the unmasked addressesresponsive to determining the second data was incorrectly stored at thesecond masked memory cells corresponding to the second masked addresses.20. The method of claim 15, further comprising reading the array ofmemory cells corresponding to each of the plurality of memory addressesto determine which of the plurality of addresses may include a defect.